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1 features ? 8-bit resolution ? adc gain adjust ? 1.5 ghz full power input bandwidth (-3 db) ? 1 gsps (min) sampling rate ? sinad = 44.3 db (7.2 effective bits), sfdr = 58 dbc, at f s = 1 gsps, f in = 20 mhz ? sinad = 42.9 db (7.0 effective bits), sfdr = 52 dbc, at f s = 1 gsps, f in = 500 mhz ? sinad = 40.3 db (6.8 effective bits), sfdr = 50 dbc, at f s = 1 gsps, f in = 1000 mhz (-3 db fs) ? 2-tone imd: -52 dbc (489 mhz, 490 mhz) at 1 gsps ? dnl = 0.3 lsb, inl = 0.7 lsb ? low bit error rate (10 -13 ) at 1 gsps ? very low input capacitance: 3 pf ? 500 mvpp differential or single-ended analog inputs ? differential or single-ended 50 ? ecl compatible clock inputs ? ecl or lvds/hstl output compatibility ? data ready output with asynchronous reset ? gray or binary selectable output data; nrz output mode ? power consumption: 3.4w at tj = 70 c typical ? radiation tolerance oriented design (150 krad (si) measured) ? two package versions ? evaluation board: tsev8388b ? demultiplexer ts81102g0: companion device available applications ? digital sampling oscilloscopes ? satellite receiver ? electronic countermeasures/electronic warfare ? direct rf down-conversion description the ts8388b is a monolithic 8-bit analog-to- digital converter, designed for digitizing wide bandwidth analog signals at very high sampling rates of up to 1 gsps. the ts8388b uses an innovative architecture, including an on-chip sample and hold (s/h), and is fabricated with an advanced high speed bipolar process. the on-chip s/h has a 1.5 ghz full power input bandwidth, providing excellent dynamic performance in undersampling applications (high if digitizing). adc 8-bit 1 gsps ts8388b rev. 2144c?bdc?04/03
2 ts8388b 2144c?bdc?04/03 functional description block diagram the following figure shows the simplified block diagram. figure 1. simplified block diagram functional description the ts8388b is an 8-bit 1 gsps adc based on an advanced high-speed bipolar technology featuring a cutoff frequency of 25 ghz. the ts8388b includes a front-end master/slave track and hold stage (s/h), followed by an analog encoding stage and interpolation circuitry. successive banks of latches regenerate the anal og residues into logical data before entering an error correction circuitry and a resynchronization stage followed by 75 ? differential output buffers. the ts8388b works in fully differential mode from analog inputs up to digital outputs. the ts8388b features a full-power input bandwidth of 1.5 ghz. a control pin gorb is provided to select either gray or bina ry data output format. a gain control pin is provided in order to adjust the adc gain. a data ready output asynchronous reset (drrb) is available on ts8388b. the ts8388b uses only vertical isolated npn transistors toget her with oxide isolated polysili- con resistors, which allow enhanced radiation tolerance (no performance drift measured at 150 krad total dose). master/slave track & hold amplifier v in , v inb clock buffer gain gorb data, datab or, orb drrb dr, drb clk, clkb 4 4 5 4 5 8 8 g=2 t/h g=1 t/h g=1 resistor chain analog encoding block interpolation stages regeneration latches error correction & decode logic output latches & buffers
3 ts8388b 2144c?bdc?04/03 specifications absolute maximum ratings note: absolute maximum ratings are limiting values (referenced to gnd = 0v), to be applied individually, while other parameters are within specified operating conditions. long exposure to maximum rating may affect device reliab ility. the use of a thermal heat sink is mandatory. see ?the board set comes fully asse mbled and tested, with the ts8388b installed.? on page 42. recommended operating conditions table 1. absolute maximum ratings parameter symbol comments value unit positive supply voltage v cc gnd to 6 v digital negative supply voltage dv ee gnd to -5.7 v digital positive supply voltage v plusd gnd -0.3 to 2.8 v negative supply voltage v ee gnd to -6 v maximum difference between negative supply voltage dv ee to v ee 0.3 v analog input voltages v in or v inb -1 to +1 v maximum difference between v in and v inb v in - v inb -2 to +2 v digital input voltage v d gorb -0.3 to v cc +0.3 v digital input voltage v d drrb v ee -0.3 to +0.9 v digital output voltage v o v plusd -3 to v plusd -0.5 v clock input voltage v clk or v clkb -3 to +1.5 v maximum difference between v clk and v clkb v clk - v clkb -2 to +2 v maximum junction temperature t j +135 c storage temperature t stg -65 to +150 c lead temperature (soldering 10s) t leads +300 c table 2. recommended operating conditions parameter symbol comments recommended value unit min typ max positive supply voltage v cc 4.5 +5 5.25 v positive digital supply voltage v plusd ecl output compatibility ? gnd ? v positive digital supply voltage v plusd lvds output compat ibility +1.4 +2.4 +2.6 v negative supply voltage v ee, dv ee -5.25-5-4.75v
4 ts8388b 2144c?bdc?04/03 electrical operating characteristics v ee = dv ee = -5v; v cc = +5v; v in -v inb = 500 mvpp full scale differential input; digital outputs 75 or 50 ? differentially terminated; tj (typical) = 70 c. full temperature range: up to -55 c < tc; tj < +125 c, depending on device grade. differential analog input voltage (full scale) v in, v inb v in - v inb 50 ? differential or single-ended 113 450 125 500 137 550 mv mvpp clock input power level p clk, p clkb 50 ? single-ended clock input 3 4 10 dbm operating temperature range t j commercial grade: ?c? industrial grade: ?v? military grade: ?m? 0 < tc; tj < 90 -40 < tc; tj < 110 -55 < tc; tj < +125 c table 2. recommended operating conditions (continued) parameter symbol comments recommended value unit min typ max table 3. electrical specifications parameter symbol test level value unit note min typ max power requirements (cbga68 package) positive supply voltage analog digital (ecl) digital (lvds) v cc v plusd v plusd 1 4 4 4.5 ? 1.4 5 0 2.4 5.5 ? 2.6 v v v positive supply current analog digital i cc i plusd 1 1 ? ? 420 130 445 145 ma ma negative supply voltage v ee 1-5.5 -5 -4.5 v negative supply current analog digital ai ee di ee 1 1 ? ? 185 160 200 180 ma ma nominal power dissipation pd 1 ? 3.9 4.1 w power supply rejection ratio psrr 4 ? 0.5 2 mw power requirements power requirements (cqfp68 packaged device) positive supply voltage analog digital (ecl) digital (lvds) v cc v plusd v plusd 1, 2, 6 4 4 4.7 ? 1.4 5 0 2.4 5.3 ? 2.6 v v v
5 ts8388b 2144c?bdc?04/03 positive supply current analog digital i cc i plusd 1, 2 6 1, 2 6 ? ? ? ? 385 395 115 120 445 445 145 145 ma ma ma ma negative supply voltage v ee 1, 2, 6 -5.3 -5 -4.7 v negative supply current analog digital ai ee di ee 1, 2 6 1, 2 6 ? ? ? ? 165 170 135 145 200 200 180 180 ma ma ma ma nominal power dissipation pd 1, 2 6 ? ? 3.4 3.6 4.1 4.3 w w power supply rejection ratio psrr 4 ? 0.5 2 mw resolution ? ? ? 8 ? bits (2) analog inputs full scale input voltage range (differential mode) (0v common mode voltage) v in v inb 4 ? -125 -125 ? ? 125 125 mv mv full scale input voltage range (single-ended input option) (see application notes) v in v inb 4 ? -250 ? ? 0 250 ? mv mv analog input capacitance c in 4? 33.5pf input bias current i in 4 ? 10 20 a input resistance r in 40.5 1 ? m ? full power input bandwidth (-3db) cbga68 package cqfp68 package fpbw ? ? ? 4 4 ? ? ? ? 1.8 1.5 ? ? ? ? ghz ghz ? small signal input bandwidth (10% full scale) ssbw 4 1.5 1.7 ? ghz clock inputs logic compatibility for clock inputs (see application notes) ?? ecl or specified clock input power level in dbm ? (10) ecl clock inputs voltages (v clk or v clkb ): ? 4???? logic ?0? voltage v il ?? ?-1.5v logic ?1? voltage v ih ?-1.1 ? ? v logic ?0? current i il ?? 5 50a logic ?1? current i ih ?? 5 50a clock input power level into 50 ? termination ? ? dbm into 50 ? ? clock input power level ? 4 -2 4 10 dbm clock input capacitance c clk 4? 33.5pf table 3. electrical specifications (continued) parameter symbol test level value unit note min typ max
6 ts8388b 2144c?bdc?04/03 digital outputs single-ended or differential input m ode, 50% clock duty cycle (clk, cl kb), binary output data format, tj (typical) = 70 c. (1)(6) logic compatibility for digital outputs (depending on the value of v plusd ) (see application notes) ? ? ecl or lvds ? differential output voltage swings (assuming v plusd = 0v): ? 4???? 75 ? open transmission lines (ecl levels) ? ? 1.5 1.620 ? v 75 ? differentially terminated ? ? 0.70 0.825 ? v 50 ? differentially terminated ? ? 0.54 0.660 ? v output levels (assuming v plusd = 0v) 75 ? open transmission lines: ? 4???? (6) logic ?0? voltage v ol ? ? -1.62 -1.54 v logic ?1? voltage v oh ?-0.88-0.8 ? v output levels (assuming v plusd = 0v) 75 ? differentially terminated: ? 4???? (6) logic ?0? voltage v ol ? ? -1.41 -1.34 v logic ?1? voltage v oh ?-1.07 -1 ? v output levels (assuming v plusd = 0v) 50 ? differentially terminated: ? ????? (6) logic ?0? voltage v ol 1, 2 6 ? ? -1.40 -1.40 -1.32 -1.25 v v logic ?1? voltage v oh 1, 2 6 -1.16 -1.25 -1.10 -1.10 ? ? v v differential output swing dos 4 270 300 ? mv output level drift with temperature ? 4 ? ? 1.6 mv/ c dc accuracy (cbga68 package) single-ended or differential input m ode, 50% clock duty cycle (clk, cl kb), binary output data format tj (typical) = 70 c. differential non linearity dnl- 1 -0.6 -0.4 ? lsb (2)(3) differential non linearity dnl+ 1 ? 0.4 0.6 lsb integral non linearity inl- 1 -1.2 -0.7 ? lsb (2)(3) integral non linearity inl+ 1 ? 0.7 1.2 lsb no missing codes ? guaranteed over specified temperature range (3) gain ? 1, 2 90 98 110 % input offset voltage ? 1, 2 -26 -5 26 mv table 3. electrical specifications (continued) parameter symbol test level value unit note min typ max
7 ts8388b 2144c?bdc?04/03 gain error drift offset error drift ? ? 4 4 100 40 125 50 150 60 ppm/ c ppm/ c dc accuracy (cqfp68 package) single-ended or differential input m ode, 50% clock duty cycle (clk, cl kb), binary output data format tj (typical) = 70 c. differential non linearity dnl- 1, 2 6 -0.5 -0.6 -0.25 -0.35 ? ? lsb lsb (2)(3) differential non linearity dnl+ 1, 2 6 ? ? 0.3 0.4 0.6 0.7 lsb lsb integral non linearity inl- 1, 2 6 -1.0 -1.2 0.7 0.9 ? ? lsb lsb (2)(3) integral non linearity inl+ 1, 2 6 ? ? 0.7 0.9 1.0 1.2 lsb lsb no missing code ? guaranteed over specified temperature range (3) gain error ? 1, 2 6 -10 -11 -2 -2 10 11 % f s % f s input offset voltage ? 1, 2 6 -26 -30 -5 -5 26 30 mv mv gain error drift offset error drift ? ? 4 4 100 40 125 50 150 60 ppm/ c ppm/ c transient performance bit error rate f s = 1 gsps f in = 62.5 mhz ber 4 ? ? 1e-12 error/ sample (2)(4) adc settling time v in -v inb = 400 mvpp ts 4 ? 0.5 1 ns (2) overvoltage recovery time tor 4 ? 0.5 1 ns (2) ac performance single-ended or di fferential input and clock mode , 50% clock duty cycle (clk, clkb), binary output data format, tj = 70 c, unless otherwise specified. signal to noise and distortion ratio sinad ????? (2) f s = 1 gsps, f in = 20 mhz 4 42 44 ? db f s = 1 gsps, f in = 500 mhz 4 41 43 ? db f s = 1 gsps, f in = 1000 mhz (-1 dbfs) 4 38 40 ? db f s = 50 msps, f in = 25 mhz 1, 2, 6 40 44 ? db table 3. electrical specifications (continued) parameter symbol test level value unit note min typ max
8 ts8388b 2144c?bdc?04/03 effective number of bits enob ????? f s = 1 gsps, f in = 20 mhz 4 7.0 7.2 ? bits f s = 1 gsps, f in = 500 mhz 4 6.6 6.8 ? bits f s = 1 gsps, f in = 1000 mhz (-1 dbfs) 4 6.2 6.4 ? bits f s = 50 msps, f in = 25 mhz 1, 2, 6 7.0 7.2 ? bits signal to noise ratio snr ????? (2) f s = 1 gsps, f in = 20 mhz 4 42 45 ? db f s = 1 gsps, f in = 500 mhz 4 41 44 ? db f s = 1 gsps, f in = 1000 mhz (-1 dbfs) 4 41 44 ? db f s = 50 msps, f in = 25 mhz 1, 2, 6 44 45 ? db total harmonic distortion thd ????? (2) f s = 1 gsps, f in = 20 mhz 4 50 54 ? db f s = 1 gsps, f in = 500 mhz 4 46 50 ? db f s = 1 gsps, f in = 1000 mhz (-1 dbfs) 4 42 46 ? db f s = 50 msps, f in = 25 mhz 1, 2, 6 46 45 ? db spurious free dynamic range sfdr ????? (2) f s = 1 gsps, f in = 20 mhz 4 52 57 ? dbc f s = 1 gsps, f in = 500 mhz 4 47 52 ? dbc f s = 1 gsps, f in = 1000 mhz (-1 dbfs) 4 42 47 ? dbc f s = 1 gsps, f in = 1000 mhz (-3 dbfs) 4 45 50 ? dbc f s = 50 msps, f in = 25 mhz 1, 2, 6 40 54 ? dbc two-tone inter-modulation distortion imd 4???? (2) f in1 = 489 mhz at f s = 1 gsps, f in2 = 490 mhz at f s = 1 gsps ? -47 -52 ? dbc switching performance and charcteristics ? see figure 2 and figure 3 on page 10 maximum clock frequency f s ?1 ?1.4gsps (14) minimum clock frequency f s 410?50msps (15) minimum clock pulse width (high) tc1 4 0.280 0.500 50 ns minimum clock pulse width (low) tc2 4 0.350 0.500 50 ns aperture delay ta 4 100 +250 400 ps (2) aperture uncertainty jitter 4 ? 0.4 0.6 ps (rms) (2)(5) data output delay tdo 4 1150 1360 1660 ps (2)(10) (11)(12) output rise/fall time for data (20% ? 80%) tr/tf 4 250 350 550 ps (11) output rise/fall time for data ready (20% ? 80%) tr/tf 4 250 350 550 ps (11) table 3. electrical specifications (continued) parameter symbol test level value unit note min typ max
9 ts8388b 2144c?bdc?04/03 notes: 1. differential output buffers are internally loaded by 75 ? resistors. buffer bias current = 11 ma. 2. see ?definition of terms? on page 48. 3. histogram testing based on samplin g of a 10 mhz sinewave at 50 msps. 4. output error amplitude < 4 lsb around corre ct code (including gain and offset error). 5. maximum jitter value obtained for single-ended clock input on the jts8388b die (chip on board): 200 fs. (500 fs expected on ts8388bg) 6. digital output back termination options depicted in application notes. 7. with a typical value of td = 465 ps, at 1 gsps, the timing safety margin for the data storing using the eclinps 10e452 out- put registers from motorola ? is of 315 ps, equally shared before and after the rising edge of the data ready signals (dr, drb). 8. the clock inputs may be indifferently ent ered in differential or single-ended, usi ng ecl levels or 4 dbm typical power level into the 50 ? termination resistor of the inphase clock input. (4 dbm into 50 ? clock input correspond to 10 dbm power level for the clock generator.) 9. at 1 gsps, 50/50 clock duty cycle, tc2 = 500 ps (tc1). t dr - tod = -100 ps (typ) does not depend on the sampling rate. 10. specified loading conditions for digital outputs: - 5 0 ? or 75 ? controlled impedance traces properly 50/75 ? terminated, or unterminated 75 ? controlled impedance traces. - controlled impedance traces far end loaded by 1 standard ecli nps register from motorola. (i.e.: 10e452) (typical input parasitic capacitance of 1.5 pf including package and esd protections.) 11. termination load parasitic capacitance derating values: - 50 ? or 75 ? controlled impedance traces properly 50/75 ? terminated: 60 ps/pf or 75 ps per additionnal eclinps load. - unterminated (source terminated) 75 ? controlled impedance lines: 100 ps/pf or 150 ps per additionnal eclinps termina- tion load. 12. apply proper 50/75 ? impedance traces propagation time derating val ues: 6 ps/mm (155 ps/inch) for tsev8388b evaluation board. 13. values for tod and tdr track each other over temperature, (1% variat ion for tod-tdr per 100 c temperature variation). therefore tod-tdr variation over temperature is negligible. moreover, the in ternal (on-chip) and package skews between each data tods and tdr effect can be considered as negligible. consequently, minimum values for tod and tdr are never more than 100 ps apart. the same is true for the tod and tdr maximum values (see advanced application notes about ?tod-tdr variation over temperature? on page 27). 14. min value guarantees performance. max value guarantees functionality. 15. min value guarantees functionality. max value guarantees performance. data ready output delay tdr 4 1110 1320 1620 ps (2)(10) (11)(12) data ready reset delay trdr 4 ? 720 1000 ps data to data ready ? clock low pulse width (see ?timing diagrams? on page 10.) tod-tdr 4 0 40 80 ps (9)(13) (14) data to data ready output delay (50% duty cycle) at 1 gsps (see ?timin g diagrams? on page 10.) td1 4 420 460 500 ps (2)(15) data pipeline delay tpd 4 4 clock cycles table 3. electrical specifications (continued) parameter symbol test level value unit note min typ max
10 ts8388b 2144c?bdc?04/03 timing diagrams figure 2. ts8388b timing diagram (1 gsps clock rate), data ready reset, cloc k held at low level figure 3. ts8388b timing diagram (1 gsps clock rate), da ta ready reset, clock held at high level tc1 tc2 ta = 250 ps tbc x x n+1 x n+2 x n+3 n digital outputs (vin, vinb) data ready (dr, drb) (clk, clkb) x n+5 n-4 n-3 n n-2 n-1 tc = 1000 ps x x n+4 tod = 1360 ps 1360 ps drrb 1 ns (min) tdr = 1320 ps tpd: 4.0 clock periods 1000 ps trdr = 720 ps n-1 td2 = tc2+tod-tdr = tc2+40 ps = 540 ps tdr = 1320 ps data data data data data data n-5 n+1 td1 = tc1+tdr-tod = tc1-40 ps = 460 ps tc1 tc2 ta = 250 ps tbc n+1 n+2 n digital outputs (vin, vinb) data ready (dr, drb) (clk, clkb) n+5 n-4 n-3 n n-1 n-2 tc = 1000 ps n+4 tod = 1360 ps 1360 ps drrb 1 ns (min) tdr = 1320 ps tpd: 4.0 clock periods trdr = 720 ps n-1 td2 = tc2+tod-tdr = tc2+40 ps = 540 ps tdr = 1320 ps data data data data data data data n-5 n+1 1000 ps x x x x x x x td1 = tc1+tdr-tod = tc1-40 ps = 460 ps
11 ts8388b 2144c?bdc?04/03 explanation of test levels notes: 1. unless otherwise specified, all tests are pulsed tests: ther efore tj = tc = ta, where tj, tc and ta are junction, case and ambient temperature respectively. 2. refer to ?ordering information? on page 50. 3. only min and max values are guaranteed (typ ical values are issuing from characterization results). functions description table 4. explanation of test levels num characteristics 1 100% production tested at +25 c (1) (for ?c? temperature range (2) ). 2 100% production tested at +25 c (1) , and sample tested at specified temperatures (for ?v? and ?m? temperature range (2) ). 3 sample tested only at specified temperatures. 4 parameter is guaranteed by design and char acterization testing (thermal steady-state conditions at specified temperature). 5 parameter is a typical value only. 6 100% production tested over specified temperature range (for ?b/q? temperature range (2) ). table 5. functions description name function v cc positive power supply v ee analog negative power supply v plusd digital positive power supply gnd ground v in , v inb differential analog inputs clk, clkb differential clock inputs differential output data port dr, drb differential data ready outputs or, orb out of range outputs gain adc gain adjust gorb gray or binary digital output select diod/drrb die junction te mperature measurement/ asynchronous data ready reset vin vinb clk clkb d0 d7 d0b d7b 16 dvee = -5v vcc = +5v vplusd = +0v (ecl) vplusd = +2.4v (lvds) ts8388b vee = -5v gnd gain gorg diod/ drrb or orb dr drb
12 ts8388b 2144c?bdc?04/03 digital output coding nrz (non return to zero) mode, ideal coding: does not include gain, offset, and linearity volt- age errors. table 6. digital output coding differential analog input voltage level digital output out of range binary gorb = vcc or floating gray gorb = gnd > +251 mv > positive full scale + 1/2 lsb 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 +251 mv +249 mv positive full scale + 1/2 lsb positive full scale - 1/2 lsb 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 +126 mv +124 mv positive 1/2 scale + 1/2 lsb positive 1/2 scale - 1/2 lsb 1 1 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 0 1 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 +1 mv -1 mv bipolar zero + 1/2 lsb bipolar zero - 1/2 lsb 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 -124 mv -126 mv negative 1/2 scale + 1/2 lsb negative 1/2 scale - 1/2 lsb 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 -249 mv -251 mv negative full scale + 1/2 lsb negative full scale - 1/2 lsb 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 < -251 mv < negative full scale - 1/2 lsb 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
13 ts8388b 2144c?bdc?04/03 package description pin description note: 1. the common mode level of the output buff ers is 1.2v below the positive digital supply. for ecl compatibility the positive digita l supply must be set at 0v (ground). for lvds compatibility (output common mode at +1.2v) the positive digital supply must be set at 2.4v. if the subsequent lvds circuitr y can withstand a lower level for input common mode, it is recommended to lower the posi- tive digital supply level in the same proportion in order to spare power dissipation. table 7. ts8388bgl pin description (cbga68 package) symbol pin number function gnd a2, a5, b1, b5, b10, c2, d2, e1, e2, e11, f1, f2, g11, k2, k3, k4, k5, k10, l2, l5 ground pins. to be connected to external ground plane. v cc a4, a6, b2, b4, b6, h1, h2, l6, l7 +5v positive supply. v ee a3, b3, g1, g2, j1, j2 5v analog negative supply. dv ee f10, f11 -5v digital negative supply. v in l3 in phase (+) analog input signal of the sample and hold differential preamplifier. v inb l4 inverted phase (-) of ecl clock input signal (clk). clk c1 in phase (+) ecl clock input signal. the analog input is sampled and held on the rising edge of the clk signal. clkb d1 inverted phase (-) of ecl clock input signal (clk). b0, b1, b2, b3, b4, b5, b6, b7 a8, a9, a10, d10, h11, j11, k9, k8 in phase (+) digital outputs. b0 is the lsb. b7 is the msb. b0b, b1b, b2b, b3b, b4b, b5b, b6b, b7b b7, b8, b9, c11, g10, h10, l10, l9 inverted phase (-) digital outputs. b0b is the inverted lsb. b7b is the inverted msb. or k7 in phase (+) out of range bit. out of range is high on the leading edge of code 0 and code 256. orb l8 inverted phase (+) out of range bit (or). dr e10 in phase (+) output of data ready signal. drb d11 inverted phase (-) output of data ready signal (dr). gorb a7 gray or binary select output format control pin. - binary output format if gorb is floating or v cc . - gray output format if gorb is connected at ground (0v). gain k6 adc gain adjust pin. the gai n pin is by default grounded, the adc gain transfer fuction is nominally close to one. diod/drrb k1 die function te mperature measurement pin and asynchronous data ready reset active low, single-ended ecl input. v plusd b11, c10, j10, k11 +2.4v for lvds output levels otherwise to gnd (2) . nc a1, a11, l1, l11 not connected.
14 ts8388b 2144c?bdc?04/03 ts8388bgl pinout figure 4. ts8388bgl pinout of cbga 68 package 1 2 3 4 5 6 7 8 9 10 11 vplusd vplusd nc b3b drb gnd gnd b4 b5 nc dvee gnd gnd b2 vplusd b3 dr b4b b5b vplusd b6b b2b b6 b1 b7b b1b b7 b0 orb b0b or gorb vcc vcc gain vcc vcc gnd gnd gnd gnd vcc gnd vcc vinb vee gnd vee vin dvee vcc gnd gnd gnd gnd gnd vee vcc vee gnd gnd gnd diode nc ball a1 index other side bottom view clk clkb gnd vee vcc vee nc gnd abcdefgh jkl
15 ts8388b 2144c?bdc?04/03 notes: 1. following pin numbers 37 (clk), 40 (clkb), 54 (v in ) and 57 (v inb ) have to be connected to gnd through a 50 ? resistor as close as possible to the package (50 ? termination preferred option). 2. the common mode level of the output buffer s is 1.2v below the positive digital supply. for ecl compatibility the positive digita l supply must be set at 0v (ground). for lvds compatibility (output common mode at +1.2v) the positive digital supply must be set at 2.4v. if the subsequent lvds circuitr y can withstand a lower level for input common mode, it is recommended to lower the posi- tive digital supply level in the same proportion in order to spare power dissipation. table 8. ts8388bf/ts8388bfs pin description (cqfp68 package) symbol pin number function gnd 5, 13, 27, 28, 34, 35, 36, 41, 42, 43, 50, 51, 52, 53, 58, 59 ground pins. to be connected to external ground plane. v plusd 1, 2, 16, 17, 18, 68 digital positive supply (0v for ecl compatibility, 2.4v for lvds compatibility). (2) v cc 26, 29, 32, 33, 46, 47, 61 +5v positive supply. v ee 30, 31, 44, 45, 48 -5v analog negative supply. dv ee 8, 9, 10 -5v digital negative supply. v in 54 (1) , 55 in phase (+) analog input signal of the sample and hold differential preamplifier. v inb 56, 57 (1) inverted phase (-) of analog input signal (v in ). clk 37 (1) , 38 in phase (+) ecl clock input signal. the analog input is sampled and held on the rising edge of the clk signal. clkb 39, 40 (1) inverted phase (-) of ecl clock input signal (clk). d0, d1, d2, d3, d4, d5, d6, d7 23, 21, 19, 14, 6, 3, 66, 64 in phase (+) digital outputs. b0 is the lsb. b7 is the msb. d0b, d1b, d2b, d3b, d4b, d5b, d6b, d7b 24, 22, 20, 15, 7, 4, 67, 65 in verted phase (-) digital outputs. b0b is the inverted lsb. b7b is the inverted msb. or 62 in phase (+) out of range bit. out of range is high on the leading edge of code 0 and code 256. orb 63 inverted phase (+) out of range bit (or). dr 11 in phase (+) output of data ready signal. drb 12 inverted phase (-) output of data ready signal (dr). gorb 25 gray or binary select output format control pin. - binary output format if gorb is floating or v cc . - gray output format if gorb is connected at ground (0v). gain 60 adc gain adjust pin. diod/drrb 49 this pin has a double function (can be left open or grounded if not used): - diod: die junction temperature monitoring pin. - drrb: asynchronous data ready reset function.
16 ts8388b 2144c?bdc?04/03 ts8388bf/ ts8388bfs pinout figure 5. ts8388bf/ts8388bfs pinout of cqfp68 package top view ts8388bf/ts8388bfs 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 vplusd vplusd vplusd vplusd d3b d3 gnd drb dr dvee dvee dvee d4b d4 gnd d5b d5 gnd gnd clk clk clkb gnd gnd clkb gnd gnd gnd vee vee vcc vcc vee diode 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 gnd vcc d2b d1 d1b vplusd d2 d0 d0b gorb vcc gnd gnd vcc vee vee vcc gnd gnd d6 d7b d7 vplusd pin 1 index d6b orb or vcc gain gnd gnd vinb vinb vin vin 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
17 ts8388b 2144c?bdc?04/03 typical characterization results static linearity f s = 50 msps/f in = 10 mhz figure 6. integral non linearity note: clock frequency = 50 msps; signal frequency = 10 mhz; positive peak: 0.78 lsb; negative peak: -0.73 lsb figure 7. differential non linearity note: clock frequency = 50 msps; signal frequency = 10 mhz; positive peak: 0.3 lsb; negative peak: -0.39 lsb
18 ts8388b 2144c?bdc?04/03 effective number of bits versus power supplies variation figure 8. effective number of bits = f (v eea ); f s = 500 msps; f in = 100 mhz figure 9. effective number of bits = f (v cc ); f s = 500 msps; f in = 100 mhz figure 10. effective number of bits = f (v eed ); f s = 500 msps; f in = 100 mhz 0 1 2 3 4 5 6 7 8 -7 -6.5 -6 -5.5 -5 -4.5 -4 veea (v) enob (bits) 0 1 2 3 4 5 6 7 8 33.544.555.566.57 vcc (v) enob (bits) 0 1 2 3 4 5 6 7 8 -6 -5.5 -5 -4.5 -4 -3.5 -3 veed (v) enob (bits)
19 ts8388b 2144c?bdc?04/03 typical fft results figure 11. f s = 1 gsps; f in = 20 mhz figure 12. f s = 1 gsps; f in = 495 mhz figure 13. f s = 1 gsps; f in = 995 mhz (-3 db full scale input)
20 ts8388b 2144c?bdc?04/03 spurious free dynamic range versus input amplitude figure 14. sampling frequency: f s = 1 gsps; input frequency f in = 995 mhz; full scale; enob = 6.4; sinad = 40 db; snr = 44 db; thd = -46 dbc; sfdr = -47 dbc; gray or binary output coding figure 15. sampling frequency: f s = 1 gsps; input frequency f in = 995 mhz; -3 db full scale; enob = 6.6; sinad = 40.8 db; snr = 44 db; thd = -48 dbc; sfdr = -50 dbc; gray or binary output coding
21 ts8388b 2144c?bdc?04/03 dynamic performance versus analog input frequency f s = 1 gsps, f in = 0 up to 1600 mhz, full scale input (f s ), f s -3 db clock duty cycle 50/50, binary/gray output coding , fully differential or single-ended analog and clock inputs. figure 16. enob (db) figure 17. snr (db) figure 18. sfdr (dbc) 3 4 5 6 7 8 0 200 400 600 800 1000 1200 1400 1600 1800 enob (db) fs input frequency (mhz) -3 db fs 30 32 34 36 38 40 42 44 46 48 50 0 200 400 600 800 1000 1200 1400 1600 1800 snr (db) fs input frequency (mhz) -3 db fs -60 -55 -50 -45 -40 -35 -30 -25 -20 0 200 400 600 800 1000 1200 1400 1600 1800 sfdr (dbc) fs input frequency (mhz) -3 db fs
22 ts8388b 2144c?bdc?04/03 effective number of bits (enob) versus sampling frequency analog input frequency: f in = 495 mhz and nyquist conditions (f in = f s /2) clock duty cycle 50/50, binary output coding figure 19. enob (db) sfdr versus sampling frequency analog input frequency: f in = 495 mhz and nyquist conditions (f in = f s /2) clock duty cycle 50/50, binary output coding figure 20. sfdr (dbc) 2 3 4 5 6 7 8 0 200 400 600 800 1000 1200 1400 1600 enob (db) sampling frequency (msps) fin = fs/2 fin = 500 mhz -60 -55 -50 -45 -40 -35 -30 -25 -20 0 200 400 600 800 1000 1200 1400 1600 sfdr (dbc) sampling frequency (msps) fin = fs/2 fin = 500 mhz
23 ts8388b 2144c?bdc?04/03 ts8388b adc performances versus junction temperature figure 21. effective number of bits versus junction temperature f s = 1 gsps; f in = 500 mhz; duty cycle = 50% figure 22. signal to noise ratio versus junction temperature f s = 1 gsps; f in = 507 mhz; differential clock; single-ended analog input (v in = -1 dbfs) figure 23. total harmonic distorsion versus junction temperature f s = 1 gsps; f in = 507 mhz; differential clock; single-ended analog input (v in = -1 dbfs) 3 4 5 6 7 8 -40 -20 0 20 40 60 80 100 120 140 160 temperature ( c) enob (bits) temperature ( c) 42 43 44 45 46 -60 -40 -20 0 20 40 60 80 100 120 snr (db) temperature ( c) 43 45 47 49 51 53 -60 -40 -20 0 20 40 60 80 100 120 thd (db)
24 ts8388b 2144c?bdc?04/03 figure 24. power consumption versus junction temperature f s = 1 gsps; f in = 500 mhz; duty cycle = 50% typical full power input bandwidth figure 25. 1.8 ghz at -3 db (-2 dbm full power input) ? cbga68 package 0 1 2 3 4 5 -40 -20 0 20 40 60 80 100 120 140 160 power consumption (w) temperature ( c) -6 -5 -4 -3 -2 -1 0 400 600 800 1000 1200 1400 1600 1800 2000 magnitude (db) frequency (mhz)
25 ts8388b 2144c?bdc?04/03 figure 26. 1.5 ghz at -3 db (-2 dbm full power input) ? cqfp68 package -6 -5 -4 -3 -2 -1 0 100 300 500 700 900 1100 1300 1500 1700 magnitude (db) frequency (mhz)
26 ts8388b 2144c?bdc?04/03 adc step response test pulse input characteristics: 20% to 80 % input full scale and rise time ~ 200 ps. note: this step response was obtained with the tsev8388b chip on-board (device in die form). figure 27. test pulse digitized with 20 ghz dso figure 28. same test pulse digitized with ts8388b adc note: ripples are due to the test setup (they are present on both measurements). 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 time (ns) tr ~ 240 ps 50 mv/div vpp ~ 260 mv 500 ps/div 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 200 150 100 50 0 adc code time (ns) tr ~ 280 ps 50 codes/div (vpp ~ 260 mv) 500 ps/div adc calculated rise time: between 150 and 200 ps
27 ts8388b 2144c?bdc?04/03 ts8388b main features timing information timing value for ts8388b timing values as defined in table 3 on page 4 are advanced data, issued from electric simula- tions and first characterizations results fitted with measurements. timing values are given at package inputs/outputs, taking in to account package internal con- trolled impedance trac es propagation delays, gullwing pin mo del, and specified termination loads. propagation delays in 50/75 ? impedance traces are not taken into account for tod and tdr. apply proper derating values corresponding to termination topology. the min/max timing values are valid over the full temperature range in the following conditions: ? specified termination load (different ial output data and data ready): 50 ? resistor in parallel with 1 standard eclin ps register from moto rola (i.e.: 10e452) typical eclinps inputs shows a typical input capacitance of 1.5 pf (including package and esd protections). if addressing an output dmux, take care if some digital outputs do not have the same termination load and apply correspo nding derating value given below. ? output termination load derating values for tod and tdr: ~ 35 ps/pf or 50 ps per additional eclinps load. ? propagation time delay derating values have also to be applied for tod and tdr: ~ 6 ps/mm (155 ps/inch) for tsev8388b evaluation board. apply proper time delay derating value if a different dielectric layer is used. propagation time considerations tod and tdr timing values are given from pin to pin and do not include the additional propagation times between device pins and input/output termination loads. for the tsev8388b evaluation board, the propagation ti me delay is 6 ps/mm (155 ps/inch) corre- sponding to 3.4 (at 10 ghz) dielectric constant of the ro4003 used for the board. if a different dielectric layer is used (for instance teflon), please use appropriate propagation time values. td does not depend on propagation times because it is a differential data (td is the time dif- ference between data ready output delay and digital data output delay). td is also the most straightforward data to meas ure, again because it is differential: td can be measured directly onto te rmination loads, with ma tched oscilloscopes probes. tod-tdr variation over temperature values for tod and tdr track each other over temperature (1% variation for tod-tdr per 100 c temperature variation). therefore tod-tdr variat ion over temperature is negligible. moreover, the internal (on-chip) and package skews between each data tods and tdr effect can be considered as negligible.
28 ts8388b 2144c?bdc?04/03 consequently, minimum values for tod and td r are never more than 100 ps apart. the same is true for the tod and tdr maximum values. in other terms : ? if tod is at 1150 ps, tdr will not be at 1620 ps (maximum time delay for tdr). ? if tod is at 1660 ps, tdr will not be at 1110 ps (minimum time delay for tdr). however, external tod-tdr values may be dictated by total digital datas skews between every tods (each digital data) and tdr: mcm board, bonding wires and output lines lengths differences, and output termination impedance mismatches. the external (on board) skew effect has not bee n taken into account fo r the specification of the minimum and maximum values for tod-tdr. principle of operation the analog input is sampled on the rising edge of external clock input (clk, clkb) after ta (aperture delay) of typically 250 ps. the digitize d data is available after 4 clock periods latency (pipeline delay (tpd)), on clock rising edge, after 1360 ps typical propagation delay tod. the data ready differential output signal frequency (dr, drb) is half the external clock fre- quency, that is it switches at th e same rate as the digital outputs. the data ready output signal (dr, drb) switches on external clock fa lling edge after a prop- agation delay tdr of typically 1320 ps. a master asynchronous reset input command drrb (ecl compatible single-ended input) is available for initializing the diff erential data ready output signal (dr, drb). this feature is mandatory in certain applications using interlea ved adcs or using a single adc with demulti- plexed outputs. actually, without data ready sign al initialization, it is impossible to store the output digital datas in a defined order. principle of data ready signal control by drrb input command data ready output signal reset the data ready signal is reset on falling edge of drrb input command, on ecl logical low level (-1.8v). drrb may also be tied to v ee = -5v for data ready output signal master reset. so long drrb remains at logical low level, (or tied to v ee = -5v), the data ready output remains at logical zero and is independant of the external free running encoding clock. the data ready output si gnal (dr, drb) is reset to logica l zero after trdr = 920 ps typical. trdr is measured between the -1.3v point of the falling edge of drrb input command and the zero crossing point of the differentia l data ready output signal (dr, drb). the data ready reset command may be a pulse of 1 ns minimum time width.
29 ts8388b 2144c?bdc?04/03 data ready output signal restart the data ready output signal restarts on d rrb command rising edge, ecl logical high levels (-0.8v). drrb may also be grounded, or is allowed to float, for normal free running data ready output signal. the data ready signal restart sequence depends on the logical level of the external encoding clock, at drrb rising edge instant: ? the drrb rising edge occurs when external encoding clock input (clk, clkb) is low: the data ready output first rising edge occurs after half a clock period on the clock falling edge, after a delay time tdr = 13 20 ps already defined hereabove. ? the drrb rising edge occurs when external encoding clock input (clk, clkb) is high: the data ready output first rising edge occu rs after one clock period on the clock falling edge, and a delay tdr = 1320 ps. consequently, as the analog input is sampled on clock rising edge, the fi rst digitized data cor- responding to the first acquisition (n) after data ready signal re start (rising edge) is always strobed by the third rising edge of the data ready signal. the time delay (td1) is specified between the last point of a change in the differential output data (zero crossing poin t) to the rising or falling edge of th e differential data ready signal (dr, drb) (zero crossing point). for normal initialization of data ready output signal, the external encoding clock signal fre- quency and level must be controlled. it is re minded that the minimum encoding clock sampling rate for the adc is 10 msps and consequen tly the clock c annot be stopped. one single pin is used for both drrb input command and die junction temperature monitor- ing. pin denomination will be drrb/diod. on the former version denomination was diod. temperature monitoring and data ready contro l by drrb is not possible simultaneously. analog inputs (v in ) (v inb ) the analog input full scale range is 0.5v peak to peak (vpp), or -2 dbm into the 50 ? termina- tion resistor. in differential mode input configuration, that means 0.25v on each input, or 125 mv around 0v. the input common mode is ground. the typical input capacitance is 3 pf for ts8388b in cqfp and cbga packages. the input capacitance is mainly due to the package. the esd protections are not connected (but present) on the inputs. differential inputs voltage span figure 29. differential inputs voltage span -125 125 [mv] -250 mv vin (vin, vinb) = 250 mv = 500 mv diff 500 mv full scale analog input t vinb 0v 250 mv
30 ts8388b 2144c?bdc?04/03 differential versus single-ended analog input operation the ts8388b can operate at full speed in either differential or single-ended configuration. this is explained by the fact the adc uses a high input impedance di fferential preamplifier stage, (preceeding the sample and hold st age), which has been designed in order to be entered either in differential mode or single-ended mode. this is true so long as the out-of-phase analog input pin v inb is 50 ? terminated very closely to one of the neighboring shield ground pins (52, 53, 58, 59) which constitute the local ground reference for the inphase analog input pin (v in ). thus the differential analog input preamplifier will fully reject the local ground noise (and any capacitively and inductively coup led noise) as common mode effects. in typical single-ended conf iguration, enter on the (v in ) input pin, with the inverted phase input pin (v inb ) grounded through the 50 ? termination resistor. in single-ended input configuration, the in-phas e input amplitude is 0.5v peak to peak, cen- tered on 0v (or -2 dbm into 50 ? ). the inverted phase input is at ground potential through a 50 ? termination resistor. however, dynamic performances can be somewh at improved by entering either analog or clock inputs in differential mode. typical single-ended analog input configuration figure 30. typical single-ended analog input configuration note: since vin and vinb have a double pad architecture, a 50 ? reverse termination is needed. fo r the cbga package, this reverse termination is already on package. clock inputs (clk) (clkb) the ts8388b can be clocked at full speed wit hout noticeable performance degradation in either differential or single-ended configuration. this is explained by the fact the adc uses a di fferential preamplifier st age for the clock buffer, which has been designed in order to be entered either in differential or single-ended mode. recommended sinewave generator characteristi cs are typically -120 dbc/hz phase noise floor spectral density, at 1 khz from carrier, assumi ng a single tone 4 dbm input for the clock signal. single-ended clock input (ground common mode) although the clock inputs were intended to be dr iven differentially with nominal -0.8v/-1.8v ecl levels, the ts8388b clock buffer can mana ge a single-ended sinewave clock signal cen- tered around 0v. this is the most convenient clock input configuration as it does not require the use of a power splitter. 50 ? (external or on package) 1 m ? 3 pf -250 250 500 mv t [mv] vin vin = 250 mv = 500 mv diff vin or vinb double pad (pins 54, 55 or 56, 57) vin or vinb 50 ? reverse termination 500 mv full scale analog input vinb = 0v vinb
31 ts8388b 2144c?bdc?04/03 no performance degradation (i.e.: due to timing ji tter) is observed in th is particular single- ended configur ation up to 1.2 gsps ny quist conditions (f in = 600 mhz). this is true so long as the inverted phase clock input pin is 50 ? terminated very closely to one of the neighboring shield ground pins, which constitutes the local ground reference for the inphase clock input. thus the ts8388b differen tial clock input buffer will fully reje ct the local ground noise (and any capacitively and inductively coupled noise) as common mode effects. moreover, a very low phase noise sinewave generator must be used for enhanced jitter performance. the typical inphase clock input amplitude is 1v peak to peak, centered on 0v (ground) com- mon mode. this corresponds to a typical clock input power level of 4 dbm into the 50 ? termination resistor. do not exceed 10 dbm to avoid saturation of the preamplifier input transistors. the inverted phase clock input is grounded through the 50 ? termination resistor. figure 31. single-ended clock input (ground common mode): vclk common mode = 0v; vclkb = 0v; 4 dbm typical clock input power level (into 50 ? termination resistor) note: do not exceed 10 dbm into the 50 ? termination resistor for sing le clock input power level. differential ecl clock input the clock inputs can be driven different ially with nominal -0.8 v/-1.8v ecl levels. in this mode, a low phase noise sinewave generat or can be used to drive the clock inputs, fol- lowed by a power splitter (hybrid junction) in order to obtain 180 degrees out of phase sinewave signals. biasing tees can be used for offseting the common mode voltage to ecl levels. note: as the biasing tees propagation times ar e not matching, a tunable delay line is required in order to ensure the signals to be 180 degrees out of phase especially at fast clock rates in the gsps range. figure 32. differential clock inputs (ecl levels) 50 ? (external or on package) 1 m ? 0.4 pf -0.5v +0.5v t [v] vclk clk or clkb double pad (pins 37, 38 or 39, 40) clk or clkb 50 ? reverse termination vclk = 0v vclk 50 ? (external or on package) 1 m ? 0.4 pf clk or clkb double pad (pins 37, 38 or 39, 40) clk or clkb -2v 50 ? reverse termination -1.8v -0.8v [mv] vclk t vclkb common mode = -1.3v
32 ts8388b 2144c?bdc?04/03 single-ended ecl clock input in single-ended configuration enter on clk (resp . clkb) pin, with the inverted phase clock input pin clkb (respectively clk) connected to -1.3v through the 50 ? termination resistor. the inphase input amplitude is 1v peak to peak, centered on -1.3v common mode. figure 33. single-ended clocl input (ecl): vclk common mode = -1.3v; vclkb = -1.3v noise immunity information circuit noise immunity performance begins at design level. efforts have been made on the design in order to make the device as in sensitive as possible to chip environment perturbations resulting from the circuit itself or induced by external cir- cuitry (cascode stages isolati on, internal damping resistors, clamps, internal (on-chip) decoupling capacitors). furthermore, the fully differential operation from analog input up to the digital outputs provides enhanced noise immunity by common mode noise rejection. common mode noise voltage induced on the differential analog and clock inputs will be can- celed out by these balanced differential amplifiers. moreover, proper active signals shielding has been provided on the chip to reduce the amount of coupled noise on the active inputs. the analog inputs and clock inputs of the ts8388b device have been surrounded by ground pins, which must be directly connec ted to the external ground plane. digital outputs the ts8388b differential output buffers are internally 75 ? loaded. the 75 ? resistors are con- nected to the digital ground pins through a -0.8 v level shift diode (see figure 34, figure 35, figure 36 on page 35). the ts8388b output buffers are designed for driving 75 ? (default) or 50 ? properly terminated impedance lines or coaxial cables. an 11 ma bias current flowing alternately into one of the 75 ? resistors when switching ensures a 0.825v voltage drop across the resistor (untermi- nated outputs). the v plusd positive supply voltage allows the adjustment of the output common mode level from -1.2v (v plusd = 0v for ecl output compatibility) to +1.2v (v plusd = 2.4v for lvds output compatibility). therefore, the single-ended output voltages vary approximately between -0.8v and -1.625v, (outputs unterminated), around -1.2v common mode voltage. -1.8v -0.8v t [v] vclk vclkb = -1.3v
33 ts8388b 2144c?bdc?04/03 three possible line driving and back-termination scenarios are proposed (assuming v plusd = 0v): 1. 75 ? impedance transmission lines, 75 ? differentially terminated (figure 34): each output voltage varies between -1v and -1 .42v (respectively +1.4v and +1v), leading to 0.41v = 0.825v in differential, around -1.2 1v (respectively +1.21v) common mode for v plusd = 0v (respectively 2.4v). 2. 50 ? impedance transmission lines, 50 ? differentially termination (figure 35): each output voltage varies between -1.02v and -1.35v (respectively +1.38v and +1.05v), leading to 0.33v = 660 mv in differential, around -1.18v (respectively +1.21v) common mode for v plusd = 0v (respectively 2.4v). 3. 75 ? impedance open transmission lines (figure 36): each output voltage varies between -1.6v and -0.8v (respectively +0.8v and +1.6v), which are true ecl levels, leading to 0.8v = 1.6v in differential, around -1.2v (respec- tively +1.2v) common mode for v plusd = 0v (respectively 2.4v). therefore, it is possible to drive directly high input impedance st oring registers, without terminating the 75 ? trans- mission lines. in time domain, that means that the incident wave will reflect at the 75 ? transmission line output and travel back to the generator (i.e.: the 75 ? data output buffer). as the buffer output impedance is 75 ? , no back reflection will occur. note: this is no longer true if a 50 ? transmission line is used, as the latter is not matching the buffer 75 ? output impedance. each differential output termination length must be kept identical. it is recommended to decou- ple the midpoint of the differential termination with a 10 nf capacitor to avoid common mode perturbation in case of slight mismatch in the differential output line lengths. too large mismatches (keep < a few mm) in the di fferential line lengths will lead to switching currents flowing into the decoupling capa citor leading to switching ground noise. the differential output voltage levels (75 ? or 50 ? termination) are not ecl standard voltage levels, however it is possible to drive standard logic ecl circuitry like the eclinps logic line from motorola ? . at sampling rates exceeding 1 gsps, it may be di fficult to trigger any acquisition system with digital outputs. it becomes necessary to regener ate digital data and data ready by means of external amplifiers, in order to be able to test the ts8388b at its optimum performance conditions.
34 ts8388b 2144c?bdc?04/03 differential output loading configur ations (levels for ecl compatibility) figure 34. differential output: 75 ? terminated figure 35. differential output: 50 ? terminated -0.8v 75 ? 75 ? - + 11 ma dvee 75 ? 75 ? impedance out outb 75 ? 75 ? -1v/-1.41v 10 nf differential output: +0.41v = 0.825v -1.41v/-1v common mode level: -1.2v (-1.2v below vplusd level) vplusd = 0v -0.8v 75 ? 75 ? - + 11 ma dvee 50 ? 50 ? impedance out outb 50 ? 50 ? -1.02v/-1.35v 10 nf differential output: +0.33v = 0.660v -1.35v/-1.02v common mode level: -1.2v (-1.2v below vplusd level) vplusd = 0v
35 ts8388b 2144c?bdc?04/03 figure 36. differential output: open loaded differential output loading configurat ions (levels for lvds compatibility) figure 37. differential output: 75 ? terminated -0.8v 75 ? 75 ? - + 11 ma dvee 75 ? 75 ? impedance out outb -0.8v/-1.6v differential output: +0.8v = 1.6v -1.6v/-0.8v common mode level: -1.2v (-1.2v below vplusd level) vplusd = 0v 1.6v 75 ? 75 ? - + 11 ma dvee 75 ? 75 ? impedance out outb 75 ? 75 ? 1.4v/0.99v 10 nf differential output: +0.41v = 0.825v 0.99v/1.4v common mode level: -1.2v (-1.2v below vplusd level) vplusd = 2.4v
36 ts8388b 2144c?bdc?04/03 figure 38. differential output: 50 ? terminated figure 39. differential output: open loaded out of range bit an out of range (or, orb) bit is provided that goes to logical high state when the input exceeds the positive fu ll scale or falls below the negative full scale. when the analog input exceeds the positive full scale, the digital output datas remain at high logical state, with (or, orb) at logical one. when the analog input falls below the negative full sc ale, the digital outputs remain at logical low state, with (or, orb) at logical one again. gray or binary output data format select the ts8388b internal regeneration latches indecisio n (for inputs very close to latches thresh- old) may produce errors in the logic encoding circuitry and leading to large amplitude output errors. this is due to the fact that the latches are regenerating the internal analog residues into logical states with a finite voltage gain value (a v) within a given posit ive amount of time ? (t): av = exp( ? (t)/ ), with the positive feedback reg eneration time constant. the ts8388b has been designed for reducing the probability of occurrence of such errors to approximately 10 -13 (targeted for the ts8388b at 1 gsps). 1.6v 75 ? 75 ? - + 11 ma dvee 50 ? 50 ? impedance out outb 50 ? 50 ? 1.38v/1.05v 10 nf differential output: +0.33v = 0.660v 1.05v/1.38v common mode level: -1.2v (-1.2v below vplusd level) vplusd = 2.4v 1.6v 75 ? 75 ? - + 11 ma dvee 75 ? 75 ? impedance out outb 1.6v/0.8v differential output: +0.8v = 1.6v 0.8v/1.6v common mode level: -1.2v (-1.2v below vplusd level) vplusd = 2.4v
37 ts8388b 2144c?bdc?04/03 a standard technique for reducing the amplitude of such errors down to 1 lsb consists of out- putting the digital datas in gray code format. though the ts8388b has been designed for featuring a bit error rate of 10 -13 with a binary output format, it is possible for the user to select between the binary or gray output data fo rmat, in order to reduce the amplitude of such errors when occurring, by storing gray output codes. digital datas format selection: ? binary output format if gorb is floating or v cc . ? gray output format if gorb is connected to ground (0v). diode pin 49 one single pin is used for both drrb input command and die junction monitoring. the pin denomination is drrb/diod. temperature monito ring and data ready control by drrb is not possible simultaneously. (see ?principle of data re ady signal control by drrb in put command? on page 28 for data ready reset input command). the operating die junction temperature must be kept below 145 c, therefore an adequate cooling system has to be set up. the diode mounted transistor measured vbe value versus junction temperature is given below. figure 40. diode pin 49 adc gain control pin 60 the adc gain is adjustable by the means of the pin 60 (input impedance is 1 m ? in parallel with 2 pf). the gain adjust transfer function is given below. 600 640 680 720 760 800 840 880 920 960 1000 -55 -35 -15 5 25 45 65 85 105 125 vbe (mv) junction temperature ( c)
38 ts8388b 2144c?bdc?04/03 figure 41. adc gain control pin 60 note: for more information, please refer to the document "demux and adcs application notes". 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 -500 -400 -300 -200 -100 0 100 200 300 400 500 adc gain vgain (command voltage) (mv)
39 ts8388b 2144c?bdc?04/03 equivalent input/output schematics figure 42. equivalent analog input cir cuit and esd protections note: the esd protection equivalent capacitance is 150 ff. figure 43. equivalent analog clock input circuit and esd protections note: the esd protection equivalent capacitance is 150 ff. vee vee 5.8v 0.8v 200 ? 200 ? 50 ? 50 ? e21v e21g e21g e21v vin gnd = 0v vinb pad capacitance 340 ff pad capacitance 340 ff vcc = +5v -0.8v -5.8v 5.8v 0.8v -0.8v -5.8v vclamp = +2.4v +1.65v -1.55v vee = -5v gnd vcc vee vee 5.8v 0.8v 150 ? 150 ? e31v e21g e21g e31v clk clkb pad capacitance 340 ff pad capacitance 340 ff vcc = +5v -5.8v -5.8v -5.8v 5.8v 0.8v -0.8v -5.8v -5.8v +0.8v gnd = 0v 380 a vee = -5v vcc
40 ts8388b 2144c?bdc?04/03 figure 44. equivalent data output buffe r circuit and esd protections note: the esd protection equivalent capacitance is 150 ff. figure 45. adc gain adjust equivalent analog input circuit and esd protections note: the esd protection equivalent capacitance is 150 ff. 5.8v 0.8v 0.8v vee vee -5.8v e21ga e01v e01v -5.8v out pad capacitance 180 ff dvee = -5v vplusd = 0v to 2.4v vee = -5v vee = -5v 5.8v 0.8v 0.8v outb pad capacitance 180 ff vee 1 k ? ga pad capacitance 180 ff 2 pf np1032c2 +0.8v 500 a 500 a vee = -5v e22v vcc = +5v gnd gnd -0.8v -5.8v 0.8v 0.8v 5.8v e22ga
41 ts8388b 2144c?bdc?04/03 figure 46. gorb equivalent input schematic and esd protections gorb: gray or binary select input; floating or tied to vcc -> binary note: the esd protection equivalent capacitance is 150 ff. figure 47. drrb equivalent input schematic and esd protections actual protection range: 6.6v above vee, in fact stre ss above gnd are clippe d by the cb diode used for tj monitoring note: the esd protection equivalent capacitance is 150 ff. 5.8v 5.8v 5.8v vee e21va -0.8v -0.8v -5.8v e31g 1 k ? 5 k ? 1 k ? 1 k ? gorb pad capacitance 180 ff vcc = +5v 250 a 250 a gnd = 0v vee = -5v 5.8v -2.6v -1.3v 0.8v 200 ? 10 k ? e21g drrb vee gnd=0v vcc = +5v vee = -5v pad capacitance 180 ff np1032c2
42 ts8388b 2144c?bdc?04/03 tsev8388b: device evaluation board for complete specific ation, see se parate tsev8388b document. general description the tsev8388b evaluation board (eb) is a boar d which has been designe d in order to facili- tate the evaluation and the char acterization of the ts8388b device up to its 1.5 ghz full power bandwidth at up to 1 gsps in the military temp erature range. the high speed of the ts8388b requires care ful attention to circuit design and layout to achieve optimal performance. this four metal layer board with internal ground plane has the adequate functions in order to allow a quick and simple evaluation of the ts 8388b adc performances over the temperature range. the tsev8388b evaluation board is very straigh tforward as it only implements the ts8388b adc, sma connectors for input/output acce sses and a 2.54 mm pitch connector compatible with high speed acquisition system probes. the board also implements a de-e mbedding fixture in order to facilitate the evaluation of the high frequency insertion loss of the input microstrip lines, and a die junction temperature mea- surement setting. the board is constituted by a sandwich of two di electric layers, featurin g low insertion loss and enhanced thermal characteristics for operati on in the high frequency domain and extended temperature range. the board dimensions are 130 mm x 130 mm. the board set comes fully assembled and tested, with the ts8388b installed.
43 ts8388b 2144c?bdc?04/03 cbga68 thermal and moisture characteristics thermal resistance from junction to ambient: rthja the following table lists the converter therma l performance parameters of the device itself, with no external heatsink added. figure 48. thermal resistance from junction to ambient: rthja thermal resistance from junction to case: rthjc typical value for rthjc is given to 6.7 c/w (8 c/w max). this value does not include thermal contact re sistance between package and external compo- nent (heatsink or pcboard). as an example, 2.0 c/w can be taken for 50 m of thermal grease. table 9. thermal resitance air flow (m/s) estimated ja thermal resistance ( c/w) 045 0.5 35.8 130.8 1.5 27.4 224.9 2.5 23 321.5 419.3 517.7 rthja ( c/w) air flow (m/s) 0 0 10 20 30 40 50 12 34 5
44 ts8388b 2144c?bdc?04/03 cbga68 board assembly with external heasink it is recommended to use an external heatsink or pcboard special design. cooling system efficiency can be monitored us ing the temperature sensing diode, integrated in the device. figure 49. cbga68 board assembly moisture characteristics this device is sensitive to the moistu re (msl3 according to jedec standard): shelf life in sealed bag: 12 months at <40 c and <90% relative humidity (rh). after this bag is opened, devices that will be subjected to infrared reflow, vapor-phase reflow, or equivalent processing (peak package body temperature 220 c) must be: ? mounted within 198 hours at factory conditions of 30 c/60% rh, or ?stored at 20% rh. devices require baking, before mounting, if humidity indicator card is >20% when read at 23 c 5 c. if baking is required, devices may be baked for: ? 192 hours at 40 c +5 c/-0 c and <5% rh for low-temperature device containers, or ? 24 hours at 125 c 5 c for high temperature device containers. 31 32.5 board 50.5 20.2 24.2
45 ts8388b 2144c?bdc?04/03 nominal cqfp68 thermal characteristics although the power dissipation is low for this performance, the use of a heat sink is mandatory. the user will find some advi ce on this topics below. thermal resistance from junction to ambient: rthja the following table lists the converter thermal performance parameters, with or without heatsink. for the following measurements, a 50 x 50 x 16 mm heatsink has been used (see figure 51 on page 46). note: 1. heatsink is glued to backside of package or screwed and pressed with thermal grease. figure 50. thermal resistance from junction to ambient: rthja table 10. thermal resitance air flow (m/s) ja thermal resistance ( c/w) cqfp68 on board estimated ? without heatsink targeted ? with heatsink (1) 050 10 0.5 40 8.9 135 7.9 1.5 32 7.3 230 6.8 2.5 28 6.5 326 6.2 424 5.8 523.5 5.6 rthja ( c/w) air flow (m/s) 0 0 10 20 30 40 50 60 123 45 without heatsink with heatsink
46 ts8388b 2144c?bdc?04/03 thermal resistance from junction to case: rthjc typical value for rthjc is given to 4.75 c/w. cqfp68 board assembly figure 51. cqfp68 board assembly with a 50 x 50 x 16 mm external heatsink 24.13 28.96 15.0 1.3 3.2 50.0 1.4 4.0 2.5 16.0 printed circuit interface: af-filled epoxy or thermal conductive grease - 100 m max. aluminum heatsink
47 ts8388b 2144c?bdc?04/03 enhanced cqfp68 thermal characteristics enhanced cqfp68 the cqfp68 has been modified, in order to improve the thermal characteristics: ? a cuw heatspreader has been added at the bottom of the package. ? the die has been electrically isolated with the aln substrate. thermal resistance from junction to case: rthjc typical value for rthjc is given to 1.56 c/w. this value does not include thermal contact re sistance between package and external compo- nent (heatsink or pcboard). as an example, 2.0 c/w can be taken for 50 m of thermal grease. heatsink it is recommended to use an external heatsink, or pcboard special design. the stand off has been calculated to permit the simultaneous soldering of the leads and of the heatspreader with the solder paste. figure 52. enhanced cqfp68 suggested assembly cooling system efficiency can be monitored us ing the temperature sensing diode, integrated in the device. printed circuit board cuw heatspreader 28.78 thermal via solid ground plane 24.13
48 ts8388b 2144c?bdc?04/03 definitions definition of terms (ber) bit error rate probability to exceed a specified er ror threshold for a sample. an error code is a code that dif- fers by more than 4 lsb from the correct code. (fpbw) full power input bandwidth analog input frequency at which the fundamental component in the digitally reconstructed out- put has fallen by 3 db with respect to its low frequency value (determined by fft analysis) for input at full scale. (sinad) signal to noise and distortion ratio ratio expressed in db of the rms signal amplitude, set to 1 db below full scale, to the rms sum of all other spectral componen ts, including the harmonics except dc. (snr) signal to noise ratio ratio expressed in db of the rms signal amplitude, set to 1 db below full scale, to the rms sum of all other spectral components excluding the five first harmonics. (thd) total harmonic distorsion ratio expressed in dbc of the rms sum of t he first five harmonic components, to the rms value of the measured fundamental spectral component. (sfdr) spurious free dynamic range ratio expressed in db of the rms signal amplitude, set at 1 db below full scale, to the rms value of the next highest spectral component (peak spurious spectral component). sfdr is the key parameter for selecting a converter to be used in a frequency domain application (radar systems, digital receiver, network analyzer, etc.). it may be reported in dbc (i.e.: degrades as signal levels is lowered), or in dbfs (i.e.: always related back to converter full scale). (enob) effective number of bits where a is the actual input amplitude and v is the full scale range of the adc under test. (dnl) differential non linearity the differential non linearity for an output code i is the difference between the measured step size of code i and the ideal lsb step size. dn l (i) is expressed in lsbs. dnl is the maximum value of all dnl (i). dnl error specificati on of less than 1 lsb guarantees that there are no missing output codes and that the transfer function is monotonic. (inl) integral non linearity the integral non linearity for an output code i is the difference between the measured input voltage at which the transition occurs an d the ideal value of this transition. inl (i) is expressed in lsbs, and is the maximum value of all |inl (i)|. (dg) differential gain the peak gain variation (in percent ) at five different dc levels for an ac signal of 20% full scale peak to peak amplitude. f in = 5 mhz (tbc). (dp) differential phase peak phase variation (in degrees) at five diff erent dc levels for an ac signal of 20% full scale peak to peak amplitude. f in = 5 mhz (tbc). (ta) aperture delay delay between the rising edge of the different ial clock inputs (clk, clkb) (zero crossing point), and the time at which (v in , v inb ) is sampled. sinad - 1.76 + 20 log (a/v/2) 6.02 enob =
49 ts8388b 2144c?bdc?04/03 (jitter) aperture uncertainty sample to sample variation in aperture delay. the voltage error due to jitter depends on the slew rate of the signal at the sampling point. (ts) settling time time delay to achieve 0.2% accuracy at th e converter output when a 80% full scale step function is applied to the differential analog input. (ort) overvoltage recovery time time to recover 0.2% accuracy at the output, after a 150% full scale step applied on the input is reduced to midscale. (tod) digital data output delay delay from the falling edge of the differential cloc k inputs (clk, clkb) (zero crossing point) to the next point of change in the differential output data (zero crossi ng) with specified load. (td1) time delay from data to data ready time delay from data transition to data ready. (td2) time delay from data ready to data general expression is td1 = tc1 + tdr - tod with tc = tc1 + tc2 = 1 encoding clock period. (tc) encoding clock period tc1 = minimum clock pulse width (high) tc = tc1 + tc2 tc2 = minimum clock pulse width (low) (tpd) pipeline delay number of clock cycles between the sampling edge of an input data and the associated output data being made available, (not taking in account the tod). for the ts8388b the tpd is 4 clock periods. (trdr) data ready reset delay delay between the falling edge of the data re ady output asynchronous reset signal (ddrb) and the reset to digital zero transition of the data ready output signal (dr). (tr) rise time time delay for the output data signals to rize from 20% to 80% of delta between low level and high level. (tf) fall time time delay for the output data signals to fall from 80% to 20% of delta between low level and high level. (psrr) power supply rejection ratio ratio of input offset variation to a change in power supply voltage. (nrz) non return to zero when the input signal is larger than the upper bound of the adc input range, the output code is identical to the maximum code and the out of range bit is set to logic one. when the input signal is smaller than the lower bound of the a dc input range, the output code is identical to the minimum code, and the out of range bit is set to logic one. (it is assumed that the input sig- nal amplitude remains within the absolute maximum ratings). (imd) intermodulation distortion the two tones intermodulation distortion (imd) reject ion is the ratio of ei ther input tone to the worst third order intermodulation products. the input tones levels are at -7 db full scale. (npr) noise power ratio the npr is measured to characterize the adc performance in response to broad bandwidth signals. when using a notch-filtered broadband white-noise generator as the input to the adc under test, the noise power ratio is defined as the ratio of the aver age out-of-notch to the average in-notch power spectral density magni tudes for the fft spec trum of the adc output sample test.
50 ts8388b 2144c?bdc?04/03 ordering information table 11. ordering information part number package temperature range screening comments jts8388b-1v1b die ambient visual inspection on request only (please contact marketing) jts8388b-1v2b die ambient and high temperature (tj = 125 c) visual inspection on request only (please contact marketing) ts8388bcf cqfp 68 c" grade 0 c < tc; tj < 90 c standard ts8388bvf cqfp 68 "v" grade -40 c < tc; tj < 110 c standard ts8388bmf cqfp 68 "m" grade -55 c < tc; tj < 125 c standard ts8388bmf b/q cqfp 68 "m" grade -55 c < tc; tj < 125 c mil-prf-38535, qml level q dscc 5962-0050401qyc ts8388bmf b/t cqfp 68 "m" grade -55 c < tc; tj < 125 c standard + 3 temperatures test (min, ambient, max) ts8388bcfs cqfp 68 with heatspreader "c" grade 0 c < tc; tj < 90 c standard ts8388bvfs cqfp 68 with heatspreader "v" grade -40 c < tc; tj < 110 c standard ts8388bmfs cqfp 68 with heatspreader "m" grade -55 c < tc; tj < 125 c standard ts8388bmfs b/q cqfp 68 with heatspreader "m" grade -55 c < tc; tj < 125 c mil-prf-38535, qml level q dscc 5962-0050401qxc ts8388bmfs b/t cqfp 68 with heatspreader "m" grade -55 c < tc; tj < 125 c standard + 3 temperatures test (min, ambient, max) ts8388bmfs9nb2 cqfp 68 with heatspreader "m" grade -55 c < tc; tj < 125 c . esa/scc9000 screening . non esa/scc qualified . level b selection . lot acceptance test 2 ts8388bmfs9nb3 cqfp 68 with heatspreader "m" grade -55 c < tc; tj < 125 c . esa/scc9000 screening . non esa/scc qualified . level b selection . lot acceptance test 3 ts8388bmfs9nc2 cqfp 68 with heatspreader "m" grade -55 c < tc; tj < 125 c . esa/scc9000 screening . non esa/scc qualified . level c selection . lot acceptance test 2 ts8388bmfs9nc3 cqfp 68 with heatspreader "m" grade -55 c < tc; tj < 125 c . esa/scc9000 screening . non esa/scc qualified . level c selection . lot acceptance test 3
51 ts8388b 2144c?bdc?04/03 ts8388bcgl cbga 68 "c" grade 0 c < tc; tj < 90 c standard ts8388bvgl cbga 68 "v" grade -40 c < tc; tj < 110 c standard tsev8388bf cqfp 68 ambient prototyp e evaluation board (delivered with heatsink) TSEV8388BFZA2 cqfp 68 ambient protot ype evaluation bo ard with digital receivers (delivered with heatsink) tsev8388bgl cbga 68 ambient protot ype evaluation board (delivered with heatsink) tsev8388bglza2 cbga 68 ambient protot ype evaluation bo ard with digital receivers (delivered with heatsink) table 11. ordering information part number package temperature range screening comments
52 ts8388b 2144c?bdc?04/03 cbga68 capacitors and resistors implant figure 53. ts8388bgl capacitors and resistors implant note: r and c are discrete components of 0603 size (1.6 x 0.8 mm). gnd 100 pf dvee clk 50 ? gnd clkb 50 ? gnd vee 100 pf gnd vcc 100 pf gnd vee 100 pf gnd gnd 100 pf gorb vcc 100 pf gnd vcc 100 pf gnd vee 100 pf gnd vcc 100 pf gnd gnd 100 pf gain gnd 50 ? vinb gnd 50 ? vin vcc 100 pf gnd only on-package marking electrically isolated 0.9 mm 0.9 mm 0.9 mm ? 7.0 mm 0.9 mm
53 ts8388b 2144c?bdc?04/03 outline descriptions figure 54. package dimension ? 68 pins cbga cbga 68 package. al203 substrate. package design. corner balls (x4) are not connected (mechanical ball). balls : 1.27 mm pitch on 11x11 grid. view balls side top side with soldered r, c devices (using solder sn/pb 63/37) balls side balls sn/pb 63/37 ai203 substrate ai203 ceramic cap. glued and embedded in substrate 0.63 0.10 all units in mm 1.45 0.12 15.00 0.15 mm 72x ? d = 0.80 0.10 mm abcdefghjkl 1 2 3 4 5 6 7 8 9 10 11 ball a1 index other side 1.27 ref 1.27 15.00 0.15 mm 7.84 7.84 - b - detail of ball x2 0.40 0.15 tab t (position of array of balls / edges a and b) (position of balls within array) - a - 0.15 0.95 max 100 pf 0.20 t - t - 50 ? 1.00 d
54 ts8388b 2144c?bdc?04/03 outline dimensions figure 55. package dimension ? 68-lead ceramic quad flat pack (cqfp) cqfp 68 top view 0.8 bcs 20.32 bsc 0.050 bcs 1.27 bsc pin n 1 index 0.023 0.002 0.58 0.05 24.13 0.152 0.950 0.006 28.78 - 29.13 1.133 - 1.147 0.13 - 0.25 0.005 - 0.010 0.70 - 0.95 0 - 8 0.027 - 0.037 0.950 0.006 24.13 0.152 1.133 - 1.147 28.78 - 29.13 0.075 0.008 1.9 0.20 0.135 max 3.43 max 0.018 - 0.035 0.46 - 0.88 m ? 0.005 z x y 0.004
55 ts8388b 2144c?bdc?04/03 figure 56. package dimension ? 68-lead enhanced cqfp with heatspreder cqfp 68 top view 0.8 bcs 20.32 bsc 0.050 bcs 1.27 bsc pin n 1 index 0.023 0.002 0.58 0.05 24.13 0.152 0.950 0.006 28.78 - 29.13 1.133 - 1.147 0.13 - 0.25 0.005 - 0.010 0.70 - 0.95 0 - 8 0.027 - 0.037 0.950 0.006 24.13 0.152 1.133 - 1.147 28.78 - 29.13 0.0310 0.787 0.0385 0.978 0.007 0.005 0.18 0.13 m ? 0.005 z x y 0.020 0.005 0.51 0.13
56 ts8388b 2144c?bdc?04/03 datasheet status description life support applications these products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. atmel customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify atmel for any damages resulting from such improper use or sale. table 12. datasheet status datasheet status validity objective specification this dat asheet contains target and goal specifications for discussion with customer and application validation. before design phase target specification this datas heet contains target or goal specifications for product development. valid during the design phase preliminary specification -site this datasheet contains preliminary data. additional data may be published later; could include simulation results. valid before characterization phase preliminary specification -site this datasheet contains also characterization results. valid before the industrialization phase product specification this data sheet contains final product specification. valid for production purposes limiting values limiting values given are in accordance with the absolute maximum rating s ystem (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at thes e or at any other conditi ons above those given in the characteristics sections of th e specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advi sory and does not form part of the specification.
printed on recycled paper. disclaimer: atmel corporation makes no warranty for the use of its products , other than those expressly contained in the company?s standar d warranty which is detailed in atmel?s terms and conditions loca ted on the company?s web site. the company assumes no responsibi lity for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time wi thout notice, and does not make any commitment to update the information contained herei n. no licenses to patents or other intellectual property of atmel are granted by the company in connection with the sale of atmel produc ts, expressly or by implicati on. atmel?s products are not aut horized for use as critical components in life support devices or systems. atmel corporation atmel operations 2325 orchard parkway san jose, ca 95131 tel: 1(408) 441-0311 fax: 1(408) 487-2600 regional headquarters europe atmel sarl route des arsenaux 41 case postale 80 ch-1705 fribourg switzerland tel: (41) 26-426-5555 fax: (41) 26-426-5500 asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel: (852) 2721-9778 fax: (852) 2722-1369 japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 memory 2325 orchard parkway san jose, ca 95131 tel: 1(408) 441-0311 fax: 1(408) 436-4314 microcontrollers 2325 orchard parkway san jose, ca 95131 tel: 1(408) 441-0311 fax: 1(408) 436-4314 la chantrerie bp 70602 44306 nantes cedex 3, france tel: (33) 2-40-18-18-18 fax: (33) 2-40-18-19-60 asic/assp/smart cards zone industrielle 13106 rousset cedex, france tel: (33) 4-42-53-60-00 fax: (33) 4-42-53-60-01 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel: 1(719) 576-3300 fax: 1(719) 540-1759 scottish enterprise technology park maxwell building east kilbride g75 0qr, scotland tel: (44) 1355-803-000 fax: (44) 1355-242-743 rf/automotive theresienstrasse 2 postfach 3535 74025 heilbronn, germany tel: (49) 71-31-67-0 fax: (49) 71-31-67-2340 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel: 1(719) 576-3300 fax: 1(719) 540-1759 biometrics/imagin g/hi-rel mpu/ high speed converters/rf datacom avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel: (33) 4-76-58-30-00 fax: (33) 4-76-58-34-80 e-mail literature@atmel.com web site http://www.atmel.com 2144c?bdc?04/03 ? atmel corporation 2003 . all rights reserved. atmel ? and combinations thereof are the registered trade- marks of atmel corporation or its subsidiaries. motorola ? is the registered trademark of motorola company. other terms and product names may be the trademarks of others.

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